This invention relates to latching circuits in integrated circuits, and more particularly, to ways of providing clock signals to the latching circuits to help logic designers improve circuit performance.
Integrated circuits typically contain combinational logic and sequential logic. Since combinational logic does not include storage elements, the output of a given combinational logic circuit is therefore determined solely by its present inputs. In contrast, sequential logic circuits contain storage elements with outputs that reflect the past sequence of their input values. As a result, the output of a sequential circuit is determined by both its present inputs and by the data stored in its storage elements.
In conventional flip-flop-based sequential logic circuits, the clock frequency must generally be slowed down sufficiently to accommodate the delay associated with the circuits' slowest combinational logic paths. Even if circuitry in a fast logic path produces a valid signal in less time than a slow logic path, that signal is not used until the edge of the next clock pulse. While the regularity imposed by conventional flip-flop circuits is beneficial for ease of circuit design, it tends to limit performance in certain situations.
Time borrowing schemes have been developed to try to address this problem. For example, time borrowing schemes have been developed in which various delays are provided in the clocks feeding the edge triggered flip-flops on a circuit. By selecting appropriate delays for the clocks, a circuit designer can configure a logic circuit so that flip-flops in slower paths have their clock edges delayed. This allows time to be borrowed from fast logic paths and provided to slow logic paths, so that the clock speed for the entire circuit need not be slowed to accommodate worst-case delays.
With these conventional time borrowing schemes, it can be difficult to obtain optimal performance due to the limited number of delays that are available from the clock network. Other such schemes for improving timing performance may have limited applicability or require unacceptably complex analysis. For example, time borrowing flip flops have been developed that provide a fixed and relatively small amount of time borrowing. These schemes cannot provide optimal performance in many circuits. Moreover, conventional time borrowing schemes may be prone to problems associated with race conditions and clock timing issues.
It is within this context that the embodiments described herein arise.